This invention relates, in general, to methods of manufacturing semiconductor integrated circuits, and more particularly, to methods of manufacturing semiconductor integrated circuits having a defect density reduction step decoupled from a step for setting a junction depth.
The manufacture of semiconductor integrated circuits includes such steps as formation of a buried layer on a semiconductor substrate, growth of an epitaxial layer over the semiconductor substrate, providing base, emitter, and collector regions in the epitaxial layer to form bipolar transistors, and providing drain, gate, and source regions in the epitaxial layer to form field effect transistors. In bipolar semiconductor integrated circuits, the buried layer reduces the collector resistance and is commonly referred to as a subcollector layer. In field effect transistors (FET's) the buried layer suppress latch-up.
Typically, the buried layer is formed by heavily doping a portion of the semiconductor substrate, oxidizing a surface of the substrate, annealing the substrate, and removing the oxide layer. Subsequently an epitaxial layer is grown over the semiconductor substrate. One method of doping the semiconductor substrate is via ion implantation. A common problem associated with buried layer formation using ion implantation is that the ion implantation process damages the semiconductor substrate. Such damage to the semiconductor substrate can propagate upward during the epitaxial growth, thereby creating defects on the surface of the epitaxial layer. One approach to decreasing the number of defects has been to oxidize the semiconductor substrate after it has been doped, but before the formation of the epitaxial layer, followed by a high temperature anneal. This technique consumes the damaged silicon region by converting it into an oxide layer which is then stripped from the semiconductor substrate. Thus, oxidation of the semiconductor substrate reduces the number of implant-created defect sites prior to epitaxial growth.
An additional benefit of the oxidation technique is that under appropriate oxidation conditions, the oxidation rate of the heavily doped regions is greater than that of adjacent lightly doped regions. The oxide formed by the differential oxidation provides a step in the silicon surface which is self-aligned to the buried layer and which may be used for alignment of subsequent masking layers. Further, the resulting differential oxide serves as a blocking mask during formation of buried layers for adjacent complementary type semiconductor devices.
A drawback of this oxidation technique is that an epitaxial layer grown over the substrate still has a significant defect density. A high temperature anneal is used to decrease the defect density. To further minimize defects, the anneal must be done at very high temperatures, resulting in buried layers that are both deep and wide. Thus, reduction in the epitaxial layer defect density and junction depth are coupled.
To minimize the junction depth, severe temperature ramp rates are often used which makes the process more susceptible to further defects associated with slip. Because of this junction depth constraint, the high temperature anneal is unable to eliminate all of the defects. As wafer sizes increase the susceptiblity to slip also increases.
Accordingly, it would be advantageous to have a method of forming a buried layer that separates epitaxial layer defect density control from the junction depth control. The technique should decrease the sheet resistance at the semiconductor substrate surface and decrease lateral spreading of the buried layer dopants. It would be of further advantage for the method to reduce overall defect density and susceptibility to slip. Such a method should maintain the advantages of the original process, e.g., those associated with differential oxidation, and be compatible with standard, large diameter wafer processing equipment.